Memory devices provide data storage for electronic systems. One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that may be erased and reprogrammed in blocks. Many modern personal computers have BIOS stored on a flash memory chip. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized, and to provide the ability to remotely upgrade the devices for enhanced features.
A typical flash memory comprises a memory array that includes a large number of non-volatile memory cells arranged in row and column fashion. The cells are usually grouped into blocks. Each of the cells within a block may be electrically programmed by charging its floating gate. The charge may be removed from the floating gate by a block erase operation.
NAND is a basic architecture of flash memory. A NAND cell unit comprises at least one select gate coupled in series to a serial combination of memory cells (with the serial combination being commonly referred to as a NAND string). The gates of the NAND string have traditionally been single level cells (SLCs), but manufacturers are transitioning to utilization of multilevel cells (MLCs) for gates of NAND strings. An SLC stores only one data bit, whereas an MLC stores multiple data bits. Accordingly, memory array density can be at least doubled by transitioning from SLCs to MLCs.
Regardless of whether devices are utilized as MLCs or SLCs, there are continuing goals to avoid parasitic capacitive coupling effects and stress-induced gate leakage, and to have a large memory window (with a memory window being the charge window that enables a non-volatile cell to be charged, and being defined by how much charge is placed on the cell within a given time). A large memory window may enable the multiple memory states of an MLC device to be clearly separated from one another.
Nanocrystal floating gate flash memories have attracted interest in recent years for their advantages over traditional EEPROMs. Using nanocrystals or quantum dots acting as a charge trapping material embedded between the control oxide and tunnel oxide may significantly improve the non-volatile charge retention time due to the effects of Coulomb blockade, quantum confinement, and reduction of charge leakage from weak spots in tunnel oxide. In addition, nanocrystal floating gate flash memories may improve flash EEPROMs in other areas, such as device scaling, erase/write/read speed, operating power and device lifetime.
Two important factors with embedded nanocrystal synthesis may be (1) the method of deposition of the nanocrystals, and (2) the size and distribution of the nanocrystals. Some methods of nanocrystal deposition include precipitation of nanocrystals from ion-implanted or silicon-rich oxide layers, aerosol deposition, chemical vapor deposition (CVD), and physical vapor deposition (PVD). These methods may be compatible with conventional CMOS high-temperature front end of the line processing but may be only limited to semiconductor type nanocrystals, rather than being also compatible with metal-containing nanocrystals, and may enable only limited control of nanocrystal size and distribution.
A new method has been developed for deposition of nanocrystals which utilizes chaperonin protein to form a template for retaining nanocrystals in desired orientations. The chaperonin-based method may enable formation of high-density nanocrystals with good distribution uniformity. However, it is difficult to incorporate protein-based methods into existing semiconductor fabrication processes.
It is desired to develop fabrication processes which enable homogeneous distribution of nanocrystals within nonvolatile memory cells. Is also desired to develop new memory cell structures which may take advantage of incorporation of nanocrystals therein.